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CXD3605R
Timing Generator for Frame Readout CCD Image Sensor
Description The CXD3605R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX406 CCD image sensor. Features * Base oscillation frequency 36MHz * High-speed/low-speed shutter function * Supports draft (octuple speed)/AF(auto focus) drive * Horizontal driver for CCD image sensor * Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX406 (Type 1/1.8, 3980K pixels) 48 pin LQFP (Plastic)
Absolute Maximum Ratings VSS - 0.3 to +7.0 * Supply voltage VDD VL -10.0 to VSS VH VL - 0.3 to +26.0 * Input voltage VI VSS - 0.3 to VDD + 0.3 * Output voltage VO1 VSS - 0.3 to VDD + 0.3 VO2 VO3 * Operating temperature Topr * Storage temperature Tstg VL - 0.3 to VSS + 0.3 VL - 0.3 to VH + 0.3 -20 to +75 -55 to +150
V V V V V V V C C
Pin Configuration
MCKO OSCO OSCI VDD5 VSS6 CKO SEN SCK CKI SSI HD VD
36 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 37 38 39 40 41 42 43 44 45 46 47 48 1 VSS1
35
34
33
32
31
30
29
28
27
26
25 24 VSS5 23 ADCLK 22 OBCLP 21 VSS4 20 CLPDM 19 PBLK 18 XRS 17 XSHD 16 XSHP 15 VDD4 14 VDD3 13 H2
Recommended Operating Conditions * Supply voltage VDDb 3.0 to 5.25 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.55 to 15.45 VL -7.0 to -8.0 * Operating temperature Topr -20 to +75
V V V V V C
2 RST
3 SNCSL
4 ID/EXP
5 WEN
6 SSGSL
7 VDD1
8 VDD2
9 RG
10 VSS2
11 VSS3
12 H1
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00Z48
CXD3605R
Block Diagram
VSS3
VSS2
XSHD
XSHP
VDD3
VDD2
VDD4
14 12 13 11 OSCI OSCO 28 27 1/2 Selector CKO 25 MCKO 30 1/2
8
9
10
15 16 17 18 21
XRS
RG
H1
H2
VSS4 19 PBLK 20 CLPDM 22 OBCLP 23 ADCLK 24 VSS5 4 5 ID/EXP WEN 41 V1A 43 V1B 39 V2 44 V3A 46 V3B 40 V4 47 SUB 42 VH 38 VM 45 VL
CKI
26
Pulse Generator
SNCSL
3
Selector
Latch
SSI 31 SCK 32 SEN 33 Selector SSGSL 6 SSG V Driver Register
RST
2
TEST1 37 TEST2 48
7 VDD1
29 VDD5
1 VSS1
36 VSS6
35 HD
34 VD
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CXD3605R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 CKO CKI OSCO OSCI VDD5 MCKO I/O -- I I O O I -- -- O -- -- O O -- -- O O O O O -- O O -- O I O I -- O
GND Internal system reset input. Normally apply reset during power-on. High: Normal operation, Low: Reset control Schmitt trigger input
Description
Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) Memory write timing pulse output. Internal SSG enable. High: Internal SSG valid, Low: External sync valid. With pull-down resistor
3.3V power supply. (Power supply for common logic block) 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. GND GND CCD horizontal register clock output. CCD horizontal register clock output. 3.3 to 5.0V power supply. (Power supply for H1/H2) 3.3V power supply. (Power supply for CDS block) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Pulse output for horizontal and vertical blanking period pulse cleaning. CCD dummy signal clamp pulse output. GND CCD optical black signal clamp pulse output. The horizontal/vertical OB pattern can be changed using the serial interface data. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. Inverter output for oscillation. Inverter input for oscillation. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. When not used, leave open or connect a capacitor. When not used, fix low.
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CXD3605R
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol SSI SCK SEN VD HD VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2
I/O I I I I/O I/O -- I -- O O O -- O O -- O O I
Description Serial interface data input for internal mode settings. Schmitt trigger input Serial interface clock input for internal mode settings. Schmitt trigger input Serial interface strobe input for internal mode settings. Schmitt trigger input Vertical sync signal input/output. Horizontal sync signal input/output. GND IC test pin 1; normally fixed to GND. GND (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD vertical register clock output. -7.5V power supply.(Power supply for vertical driver) CCD vertical register clock output. CCD electronic shutter pulse output. IC test pin 2; normally fixed to GND. With pull-down registor With pull-down resistor
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CXD3605R
Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 VDD2 VDD3 VDD4 VDD1, VDD5 Pins Symbol VDDa VDDb VDDc VDDd (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.2VDDd 0.7VDDd 0.2VDDd 0.8VDDd 0.2VDDd Feed current where IOH = -1.2mA VDDd - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -22.0mA VDDb - 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = -3.3mA VDDa - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = -8.25V V1A/B, V2, V3A/B, V4 = -0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = -8.25V SUB = 14.75V VDDd - 0.8 0.4 VDDd - 0.8 0.4 VDDd - 0.8 0.4 10.0 -5.0 5.0 -7.2 5.4 -4.0 VDDc - 0.8 0.4 0.4 0.4 0.4 Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.25 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
RST, SSI, SCK, Input voltage 1 1 SEN
Vt+ Vt- TEST1, TEST2, VIH1 Input voltage 2 2 SNCSL, SSGSL VIL1 VIH2 VIL2 Input/output VD, HD voltage VOH1 VOL1 VOH2 Output H1, H2 voltage 1 VOL2 VOH3 Output RG voltage 2 VOL3 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 XSHP, XSHD, VOH4 XRS, PBLK, OBCLP, CLPDM, VOL4 ADCLK CKO MCKO ID/EXP, WEN V1A, V1B, V3A, V3B, V2, V4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL IOSH
Output current 1
Output current 2
SUB
1 This input pin is a schmitt trigger input. 2 This input pin is with pull-down registor in the IC. Note) The above table indicates the condition for 3.3V drive.
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CXD3605R
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL Conditions
(Within the recommended operating conditions) Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V MHz
OSCO
Feed current where IOH = -3.6mA VDDd - 0.8 Pull-in current where IOL = 2.4mA VIN = VDDd or VSS
OSCI, OSCO RFB OSCI, OSCO f
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = -7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Note) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. -6-
CXD3605R
Switching Waveforms
TTMH 90%
TTHM VH 90%
V1A (V1B, V3A, V3B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4) 10% 90%
TTML
VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VM VCMH VCML
VCLH VCLL VL
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CXD3605R
Measurement Circuit
Serial interface data CKI C6
VD HD +3.3V -7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD3605R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C6 C6 C6 C6 C6 C6 C6 C6
C2 C2
R1
C4
C5
C1 R1
3300pF 30
C2 R2
560pF 10
C3
820pF
C4
8pF
C5
215pF
C6
10pF
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CXD3605R
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDd SSI SCK SEN SEN ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1
(Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns
ts1 th1 ts2 ts3
Serial interface clock internal loading characteristics (1)
Example: During frame mode VD HD
V1A Enlarged view HD
0.2VDDd
V1A ts1 SEN 0.8VDDd 0.2VDDd th1
Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HD SEN hold time, activated by the falling edge of HD -9- Min. 0 110 Typ. Max. Unit ns s
ts1 th1
CXD3605R
Serial interface clock internal loading characteristics (2)
Example: During frame mode VD HD Enlarged view
VD HD
0.2VDDd
ts1 SEN 0.8VDDd
th1 0.2VDDd
Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VD SEN hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns
ts1 th1
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3605R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3605R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN
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CXD3605R
RST loading characteristics
RST
0.8VDDd 0.2VDDd tw1
(Within the recommended operating conditions) Symbol Definition RST pulse width Min. 25 Typ. Max. Unit ns
tw1
VD and HD phase characteristics
VD
0.2VDDd ts1 th1 0.2VDDd
0.2VDDd
HD
(Within the recommended operating conditions) Symbol Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD Min. 100 20 Typ. Max. Unit ns ns
ts1 th1
HD loading characteristics
HD
0.2VDDd ts1 th1 0.8VDDd
0.2VDDd
MCKO
MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HD setup time, activated by the rising edge of MCKO HD hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns
ts1 th1
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CXD3605R
Output variation characteristics
MCKO
0.8VDDd
WEN, ID/EXP tpd1
WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns
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CXD3605R
Description of Operation Pulses output from the CXD3605R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 ACT ACT L L -- ACT ACT ACT ACT ACT L L L L L -- L L H ACT ACT ACT L L -- -- L L L L L ACT ACT ACT H H ACT L -- -- L L ACT ACT ACT ACT ACT ACT ACT ACT ACT L L ACT -- -- L ACT CAM SLP -- ACT ACT L L ACT L ACT L L ACT STB RST Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI OSCO OSCI VDD5 MCKO SSI SCK SEN VD1 HD1 VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 ACT ACT VH VH -- ACT ACT VH VH -- VH VH VL VL ACT ACT ACT VM VM VH -- VH VH VM VL ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L -- -- -- VM VM VH VM VL VM CAM ACT ACT ACT ACT SLP ACT ACT ACT ACT -- L ACT ACT ACT L L ACT DIS DIS DIS H H STB L ACT ACT ACT RST ACT ACT ACT ACT
1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45), respectively, in the controlled status.
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CXD3605R
Serial Interface Control The CXD3605R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.
SSI SCK SEN
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
These are two categories of serial interface data: the CXD3605R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
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CXD3605R
Control Data Data D00 to D07 D08 to D09 D10 to D12 D13 D14 D15 to D16 D17 D18 to D31 D32 D33 D34 to D35 D36 to D37 D38 to D39 D40 to D47 FGOB EXP PTOB NTPL -- Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 0 0 All 0 0 All 0 0 0 All 0 1 LDAD ADCLK logic phase adjustment See D36 to D37 LDAD. 0 All 0 All 0
10000001 Enabled Other values Disabled
CTG
Category switching
See D08 to D09 CTG.
MODE SMD HTSG --
Drive mode switching Electronic shutter mode switching1 HTSG control switching1 -- SSG function switching -- Wide OBCLP generation switching ID/EXP output switching OBCLP waveform patterm switching
See D10 to D12 MODE. OFF OFF -- NTSC -- OFF ID ON ON -- PAL -- ON EXP
See D34 to D35 PTOB.
STB
Standby control
See D38 to D39 STB.
--
--
--
--
1 See D13 SMD.
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CXD3605R
Shutter Data Data D00 to D07 D08 to D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled
CTG
Category switching
See D08 to D09 CTG.
SVD
Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification
See D10 to D19 SVD.
SHD
See D20 to D31 SHD.
SPL
See D32 to D41 SPL.
--
--
--
--
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CXD3605R
Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD3605R by the serial interface, the CXD3605R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode
Note that the CXD3605R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode] The CXD3605R drive mode can be switched as follows. However, the drive mode bits are located to the CXD3605R and reflected at the falling edge of VD. D12 0 0 0 0 D11 0 0 1 1 D10 0 1 0 1 Description of operation Draft mode (default) AF1 mode AF2 mode Frame mode D12 1 1 1 1 D11 0 0 1 1 D10 0 1 0 1 Description of operation Draft mode Frame mode (A field read out) Frame mode (B field read out) Test mode
Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (AF). AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these modes, the screen is swept in the vertical direction and the center portion lines are cut out. Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A B A and so on. Frame mode (A or B Field) is the drive mode in which each field can be specified separately. Control data: D17 NTPL [SSG function switching] The CXD3605R internal SSG output pattern can be switched as follows. However, the SSG function switching bits are loaded to the CXD3605R and reflected at the falling edge of VD. D17 0 1 Description of Operation NTSC equivalent pattern output PAL equivalent pattern output
VD period in each pattern is defined as follows. Frame mode NTSC equivalent pattern PAL equivalent pattern 1012H + 1672ck 944H + 464ck Draft mode 224H + 1372ck x 2 269H + 2039ck AF1 mode 112H + 1372ck 134H + 2354ck AF2 mode 56H + 686ck 67H + 1178ck
See the Timing Charts for the actual operation. - 17 -
CXD3605R
Control data: D32 FGOB [Wide OBCLP generation] This controls wide OBCLP generation during the vertical OPB period. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide OBCLP generation OFF Wide OBCLP generation ON
Control data: D34 to D35 PTOB [OBCLP waveform pattern] This indicates the OBCLP waveform pattern. The default is "Normal". D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide)
Control data: D36 to D37 LOAD [ADCLK logical phase] This indicates the ADCLK logic phase adjustment data. The default is 90 relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment () 0 90 180 270
Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3605R and control is applied immediately at the rising edge of SEN. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode
See the Pin Status Table for the pin status in each mode.
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CXD3605R
Control data/shutter data: [Electronic shutter] The CXD3605R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 0 1 D29 0 D28 1 D27 1 D26 1 C D25 0 D24 0 D23 0 D22 0 3 D21 1 LSB D20 1 SHD is expressed as 1C3h .
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h SVD 3FFh) Number of horizontal periods specification (000h SHD 7FFh) Vertical period specification for high-speed shutter operation (000h SPL 3FFh)
Note) The bit data definition area is assured in terms of the CXD3605R functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) - (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses - 1). - 19 -
CXD3605R
VD
SHD
SVD
V1A SUB WEN EXP SMD SVD SHD 1 002h 10Fh 1 000h 050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa.
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CXD3605R
[HTSG control mode] This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG. D14 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode
VD
V1A SUB Vck WEN EXP HTSG SMD 0 1 1 0 0 1
Exposure time
[EXP pulse] The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation. Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the latter value is 1416ck.
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Chart-1
* ICX406
Vertical Direction Timing Chart
MODE Frame mode
A Field B Field
Applicable CCD image sensor
VD
75 82 943 1013 1 74 82
943
1013 1
HD
SUB A C
High-speed sweep block
C
High-speed sweep block
B
V1A
V1B
V2
V3A
1712
1714
1716
1718
1720
1709
1711
1713
1715
1547
CCD OUT
PBLK
OBCLP
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units.
1719
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1 3 5 7 9 11 1 3 5 7 9 11
V3B
V4
2 4 6 8 10 12 2 4 6 8
CXD3605R
Chart-2
* ICX406
Vertical Direction Timing Chart
MODE Draft mode
Applicable CCD image sensor
VD
218 3 3 226 1 218 226 1
HD
SUB D D
V1A
V1B
V2
V3A
1706 1710
1713 1717
1706 1710
PBLK
OBCLP
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck units.
1713 1717
- 23 -
10 5 14 21 30 37 46 1 6 1 10 17 26 33 42
V3B
V4
10 5 14 21 30 37 46 1 6 1 10 17 26 33 42
CCD OUT
CXD3605R
Chart-3 AF1 mode
* ICX406
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VD
113 9 2 106 113 2 9
106
HD
SUB E F Frame shift block G
High-speed sweep block
G
High-speed sweep block
E
F Frame shift block
V1A
V1B
V2
V3A
- 24 -
10 6
V3B
V4
10 6
CCD OUT
PBLK
OBCLP
CLPDM
ID/EXP
WEN

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units.
CXD3605R
Chart-4
* ICX406
Vertical Direction Timing Chart
MODE AF2 mode
Applicable CCD image sensor
VD
57 12 2 47 57 2 12
47
HD
SUB E
Frame shift block Frame shift block
G
High-speed sweep block
F
G High-speed sweep block E
F
V1A
V1B
V2
V3A
- 25 -
10 6
V3B
V4
10 6
CCD OUT
PBLK
OBCLP
CLPDM
ID/EXP
WEN

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units.
CXD3605R
Chart-5 Frame mode
* ICX406
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
(2669) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
317 345 361 365
4
60
H1
H2
92 156 220 124 168 343 232 284 252 188
V1A/B
V2
60
V3A/B
V4
SUB
60
- 26 -
347 319 124 124 343
PBLK
24
50
OBCLP (1)
16
42
OBCLP (2)
32
58
OBCLP (3)
16
58
OBCLP (4)
58
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
CXD3605R
Chart-6
* ICX406
Horizontal Direction Timing Chart
MODE Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor
(2669) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
317 345 361 365
4
60
H1
H2
92 84 100 116 168 343 232 140 180 204 244 268 308 124 164 188 228 252 292 108 148 172 212 236 276 300 132 156 196 220 260 284
68
V1A/B
V2
60
V3A/B
76
V4
SUB
60
- 27 -
347 319 124 124 343
PBLK
24
50
OBCLP (1)
16
42
OBCLP (2)
32
58
OBCLP (3)
16
58
OBCLP (4)
58
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
CXD3605R
Chart-7
* ICX406
Horizontal Direction Timing Chart (High-speed sweep: C)
MODE Frame mode
Applicable CCD image sensor
(2669) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
317 345 361 365
4
60
H1
H2
116 144 116 144 200 256 312 368 172 228 284 340 396 424 200 256 312 368 424 452 480 172 228 284 340 396 452 480 508 536 508 536 564 564
60
V1A/B
88
V2
60
V3A/B
88
V4 #1
168 232
#2
#3
#4
#5
- 28 -
SUB
PBLK
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739).
CXD3605R
Chart-8
* ICX406
Horizontal Direction Timing Chart (Frame shift: F) (High-speed sweep: G)
MODE AF1 mode, AF2 mode
Applicable CCD image sensor
(2669) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
317 345 361 365
4
60
H1
H2
92 108 100 116 140 180 204 244 268 308 332 372 396 124 164 188 228 252 292 316 356 380 148 172 212 236 276 300 340 364 404 428 420 444 436 460 132 156 196 220 260 284 324 348 388 412 452 476 468 492 484 508 500 524 516 540 532 556 548
68
V1A/B
84
V2
60
V3A/B
76
V4 #1
168 232
- 29 -
#2 #3 #4 #5
124
#6
#7
#8
SUB
60
PBLK
24
50
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode. In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode.
CXD3605R
Chart-9
* ICX406
Horizontal Direction Timing Chart
MODE Frame mode
Applicable CCD image sensor
1104
1136
1168
1200 1202 1260
1292
124
156
188
220
252
(2669) 0
(2669) 0
HD A
[A Field]
V1A
V1B
V2
V3A
V3B
V4
[B Field]
B
V1A
V1B
V2
V3A
V3B
V4
The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing.
284
- 30 -
CXD3605R
Chart-10
* ICX406
Horizontal Direction Timing Chart
MODE Draft mode
Applicable CCD image sensor
1104
1136
1168
1200 1202
1260
1292
1324
1356 1358
1416
(2669) 0 60 76 92 108 124 140 156 172
(2669) 0
HD D
V1A
V1B
V2
V3A
- 31 -
V3B
V4
The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing.
68 84 100 116 132 148 164 180
CXD3605R
Chart-11
* ICX406
Horizontal Direction Timing Chart
MODE AF1 mode, AF2 mode
Applicable CCD image sensor
1104
1136
1168
1200 1202
1260
1292
1324
1356 1358
1416
1448 1464 1456 1480 1472 1496 1488 1512 1504 1528 1520 1544 1536 1560 1552 1568
(2669) 0
(2669) 0
HD E
V1A
V1B
V2
V3A
- 32 -
V3B
V4
The HD of this chart indicates the actual CXD3605R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). Internal SSG is at this timing.
60 76 92 108 124 140 156 172 188 204 220 236 252 268 284 300
68 84 100 116 132 148 164 180 196 212 228 244 260 276 292 308
CXD3605R
Chart-12
* ICX406
High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
HD
HD'
CKI
CKO
ADCLK
60 317
1
MCKO
H1
- 33 -
H2
RG
XSHP
XSHD
XRS
HD' indicates the HD which is the actual CXD3605R load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface data. CXD3605R
Chart-13
* ICX406
Vertical Direction Sequence Chart
MODE Draft Frame Draft
Applicable CCD image sensor
VD
V1A
V1B
V2
V3A
V3B
V4
- 34 -
Close B B 0 1 050h 050h 050h 1 1 0 0 C E 3 0 000h C D E
SUB Open F E 3 0 000h 0 1 050h F 0 1 050h
Mechanical shutter
Exposure time
A
CCD OUT
A
MODE
0
0
SMD
1
1
SHD
050h
050h

This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD3605R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same.
CXD3605R
CXD3605R
Application Circuit Block diagram
CCD ICX406
CCD OUT
CDS/ADC Block
D OUT
CLPDM
OBCLP
H1 H2 RG V1A V1B V2 V3A V3B V4 SUB
16 17 18 19 20 22 23 12 13 9 25 41 43 39 44 46 40 47 26 27 28 37 48 31 32 33 V-Dr TG CXD3605R 30 34 SSG 35 2 3 6 4 5 ID/EXP WEN CKO MCKO VD HD RST SNCSL SSGSL Signal Processor Block 15.0V 0V -7.5V
CKI OSCO
SSI
ADCLK SCK SEN
XSHD
XSHP
TEST1
PBLK
XRS
TEST2
OSCI
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on Of the three -7.5V, +15.0V, -3.3V power supplies, be sure to start up the -7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
t1
20%
20%
t2 t2 t1
- 35 -
CXD3605R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
0.18 0.03
0 to 10
0.5 0.2
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g
- 36 -
0.127 0.04
Sony Corporation

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